Fabrication processes of semiconductor devices include a process of testing electrical characteristics of each of multiple semiconductor chips after the chips are formed on a semiconductor wafer.
Conventionally the semiconductor chips are tested sequentially one by one.
This method, however, requires too much time to test all the semiconductor chips in the semiconductor wafer.
Accordingly, in recent years, a testing method has been developed in which reduction of testing time is achieved by installing built-in-self-test (GIST) circuits in respective semiconductor chips formed on a semiconductor wafer.
However, with an increase in the number of semiconductor chips formed on a single semiconductor wafer and an increase in the number of test items due to an increased number of functionalities of semiconductor devices, it still takes much time to test the semiconductor chips. Hence, there are increasing demands for shortening the testing time.